1. Field of the Invention
The invention relates to the field of dielectric layers employed within a microelectronics fabrication. More particularly, the invention relates to silicon oxide dielectric layers employed as barrier layers within microelectronics fabrications.
2. Description of the Related Art
Microelectronics fabrication are formed from microelectronics substrates upon which are formed patterned microelectronics conductor layers which are separated by microelectronics dielectric layers. As the dimensions of microelectronics fabrications have decreased. The sensitivity of electronic devices within the microelectronics fabrications to electrical charge re-arrangement due to mobile ionic charge migration becomes critical to stability of device operating parameters.
The presence of "hot carriers," i.e. energetic electrons which can be injected across potential barriers due to their excess energy and are then trapped adjacent to the interfaces between semiconductor and silicon oxide gate oxide insulator layer of a field effect transistor (FET) device, can cause drifts in the FET threshold voltage V.sub.t, saturation current I.sub.sat and substrate leakage current I.sub.sub parameters. In particular, hot carrier concentrations at the semiconductor interface increase the electron-hole recombination rate, thus increasing the substrate leakage current I.sub.sub. Such hot carrier injection effects result in degradation of device parameters after relatively short times of operation. Movement of mobile ions in the dielectric layer causes re-arrangement of the space charge therein which affects charge carriers in the semiconductor and can cause increased injection and trapping of hot electrons. The concentration of ions within the dielectric layer is controlled by reducing impurities, but problems remain with ions such a H.sup.+ and Na.sup.+, species which are difficult to eliminate entirely.
Silicon oxide dielectric materials are highly suited for employment as dielectric layers within microelectronics fabrications because they can be formed with high purity and generally exhibit low mobility and resistance to diffusion of most ionic species. Silicon oxide dielectric layers formed employing plasma enhanced chemical vapor deposition (PECVD) methods are found to have superior properties with respect to density, chemical purity and stability, but result in conformal layers when deposited over topographic features. In addition, the plasma exposure of the dielectric layer occurring during deposition can result in formation of electrically charged species within the dielectric layer which remain after deposition, even in the highest purity dielectric layers.
In order to obtain silicon oxide dielectric layers with more planarized surfaces for use, for example, an inter-level metal dielectric (IMD) layers, methods have been disclosed which operate at higher pressures such as ozone assisted near-atmospheric pressure chemical vapor deposition (APCVD) methods employing tetra-ethyl-ortho-silicate (TEOS) vapor. Such methods cannot employ plasma enhancement because of the high pressure of the gases involved. Thus, the silicon oxide and silicon containing glass dielectric materials formed by such methods, despite their more planar surfaces, are generally of somewhat lesser quality with respect to density, purity, stability, dielectric properties and ionic mobilities.
Methods and materials which are employed to reduce the mobility of ionic species in silicon oxide and silicon containing glass dielectric materials include doping the silicon oxide and silicon containing glass dielectric material with species such as boron and phosphorus which tend to immobilize impurity ionic species such as H.sup.+ and Na.sup.+ ions. However, the degree of immobilization of ionic species is highly dependent on the details of fabrication of the dielectric material, and some mobile ions may still diffuse into the vicinity of the gate oxide insulating layer where their space charge affects the semiconductor surface charge density at the gate insulator-semiconductor interface.
It is therefore towards the goals of forming upon a substrate within a microelectronics fabrication a silicon oxide dielectric layer with adequate density and reduced ionic concentration and ionic mobility to attenuate hot carrier injection and device degradation that the present invention is generally and more specifically directed.
Various methods have been disclosed for forming silicon oxide dielectric materials with superior qualities for employment in microelectronics fabrications.
For example, Wang et al., in U.S. Pat. No. 5,354,715, disclose a method for forming a silicon dioxide dielectric layer whose highly conformal nature affords improved step coverage as well as subsequent planarization over topography of surfaces of microelectronics fabrications. The method employs O.sub.3 and O.sub.2 gases and TEOS vapor in a plasma at relatively high pressure and low chamber temperature to form the conformal silicon dioxide layer at a high rate and low temperature, followed by an isotropic etch in the same chamber to further improve planarization.
Further, Wang et al., in U.S. Pat. No. 5,362,526, disclose a method for forming silicon dioxide dielectric layers with conformal though planarized surfaces. The method employs O.sub.3 and TEOS gases in a plasma in a relatively high pressure, low temperature reactor to form silicon dioxide layers at a high rate and a subsequent isotropic etch in the same reactor to effect planarization.
Finally, Wann et al., in U.S. Pat. No. 5,811,343, disclose a method for forming a blanket silicon oxide layer over a silicon nitride layer formed upon an oxidized polysilicon layer from which fluorine has been removed by gettering into the sacrificial polysilicon oxide getter layer. The blanket silicon oxide layer passivates the silicon nitride-polysilicon layer, and it is formed employing TEOS and O.sub.2 in a chemical vapor deposition (CVD) process.
Desirable in the art of microelectronics fabrication are additional methods for providing silicon oxide dielectric layers with improved quality and purity and hence reduced mobile species, ionic concentration and ionic mobility, providing FET device resistance to hot carrier injection effects and purity of silicon oxide adjacent to gate oxide insulation layer and semiconductor channel regions of FET devices.
It is towards these goals that the present invention is generally and specifically directed.